SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.

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Each bit combination that comes out of the output lines is called a word. Write down the expression for worst case delay for RCA. By using sleep transistors to isolate the supply from the block to achieve significant leakage power savings.

Enter the email address you signed up with and we’ll clsi you a reset link. Multiplexing element of path selector A latch element an unlock switch Act as a voltage controlled resistor connecting the input vosi output. A fundamental difficulty with dynamic circuits is a loss of noise immunity and a serious timing restriction on the inputs of the gate. Read operation is destructive. This provides sufficient power saving. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

Static power due to Sub threshold conduction through OFF transistors Tunneling mwrks through gate oxide Leakage through reverse biased diodes Contention current in radioed circuits.

It will determine whether the fault coverage exceeds a desired level. What are the steps involved in twin tub process?


Give some of the important CAD tools. Needs a precharge clock. A device connected so as to pull the output voltage to the lower supply voltage usually 0 V is called pull down device. Design turnaround is a few hours. Skip to main content. What is pull up device?

EC – VLSI Design TWO MARKS WITH ANSWERS | Manoharan K. –

List the advantages of pass transistor logic. Information is lost if power line is removed. Low answerx Dissipation High Packing density Bi directional capability Also it is the cartoon of a chip layout. What are the uses of Stick diagram? Green — n-diffusion Red- polysilicon Blue —metal Yellow- implant Black-contact areas.

What are the value sets in Verilog? What is a multiplier circuit? What are the scan-based test techniques? The Test Access Port TAP is a definition of the interface that needs to be included in an IC to make it capable of being included in a boundary-scan architecture. What is the logic of adder for increasing its performance? No Latch Flip Flop 1. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.

Only the interconnect is customized Only the top few mask layers customized. Level-sensitive timing control 49 Give the different arithmetic operators?

What are the general properties of elmore delay model? Write notes on manufacturing tests? Differentiate between channeled and channel less gate array.



Pass transistor logic circuits are often superior to standard CMOS circuits in terms of layout density, circuit delay and power consumption. What are the steps performed to achieve lithography friendly anewers Give the variety of integrated circuits ICs.

If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped. Output signal start to change after its input change and settles to the final value within propagation delay. Setup time is a requirement that the data has to be stable before the clock edge wirh hold time is a requirement that the data has to be stable after the clock edge.

The carry skip adder is shown to be superior to constant width carry skip module the advantages being greater at high precisions. The current between drain and source terminals is constant and independent of the applied voltage over the terminals.

Enter the email address you signed up with and we’ll email you a reset link. This is not entirely correct. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design.